The realization of very large time constant circuits (circuits which have a very large ratio between the operating clock frequency and the pole/zero frequencies) is a bottleneck in the design of many analog integrated circuits. Examples of this in voice-band circuits are power supply rejection filters, such as 60 Hz/180 Hz notch filters and automatic gain control loop filters which have pole frequencies of a few Hz. The clock frequencies used for these filters are usually much higher, for example, 128 KHz, as determined by the rest of the switched-capacitor circuitry in the system.
The preferred technology for realizing switched capacitor circuits has been and is presently metal oxide semiconductor (MOS) technology. There have been a number of solutions to the problem of designing such circuits using the MOS technology. A paper entitled "Switched-Capacitor Circuit Design" by R. Gregorian et al., Proceedings of the IEEE, Vol. 71, August 1983, pp. 941-966, surveys the field. In general, the realization of a MOS switched capacitor circuit having a large integrating time constant is achieved by replacing the input resistor of a conventional active RC integrator with a capacitive network that simulates a resistance. One such network consists of two transistor switches serially connected to an input of an operational amplifier and a capacitor connected from the common point between the switches to ground. The two switches are operated in different clock phases. The integrating time constant thus obtained depends inversely on the operating clock frequency and proportionally on the ratio of the integrating capacitance in shunt with the amplifier and the effective switched input capacitance.
Lowering the clock frequency to achieve larger time constants in the above circuit is not a viable alternative in many applications. Thus, the ratio of integrating capacitance to input capacitance must be increased. Decreasing the input capacitance to increase this ratio is not desirable because parasitic capacitances then begin to play a dominant role. Thus, the integrating capacitance must be increased. This solution, however, requires large amounts of chip area.
The problems of the above-described arrangement led to the use of the now standard input T-capacitor network. This arrangement is discussed in a paper entitled "An Area-Efficient Approach to the Design of Very Large Time Constants in Switched-Capacitor Integrators" by Sansen et al., IEEE Journal of Solid-State Circuits, Vol. SC-19, October 1984, pp. 772-779. The T-network approach has the advantage that it can easily be mixed with conventional switched-capacitor circuitry. However, it suffers from a strong sensitivity to parasitic capacitances, thus causing significant deviations in the time constant of the integrator. The high parasitic sensitivity places constraints on the design and layout of circuits using these integrators. This partially nullifies the area advantage of the technique.
Other known approaches for realizing very large time constants suffer from more serious limitations. A method proposed by M. Yamamoto, "Large Time-Constant SC Circuits and Uni-Value Capacitor SC Circuits Using Multi-Phase Clock", Proceedings of the IEEE, International Symposium on Circuits and Systems, May 1982, is parasitic-sensitive, apart from requiring a multi-phase clock. An approach given by Viswanathan et al., "Increasing the Clock Frequency of Switched-Capacitor Filters", Electronic Letters, Vol. 16, 1980, relies on switching in more than two clock phases and does not yield simple circuits. Also, the way the switching is performed between the separate functions of input attenuation and integration results in an undesirable slewing of its output.